1. Field of the Invention
The present invention pertains to the field of emulator design. More particularly, this invention relates to the art of interconnecting the logic elements of an emulator system.
2. Background
With advances in integrated circuit technology, various tools have been developed to aid circuit designers in designing and debugging highly complex integrated circuits. In particular, emulation systems comprising reconfigurable logic elements have been developed for circuit designers to quickly "realize" their designs and emulate operation of the circuits.
Early emulation systems include relatively small number of logic elements, in today's standard. Typically the logic elements are disposed in general purpose field programmable gate arrays (FPGAs). The FPGAs in turn are arranged into a 2-D or 3-D array, and interconnected together directly in a "nearest neighbor" manner or indirectly using full or partial crossbars made of programmable interconnect chips. As is well known in the art, the programmable interconnect paths between the logic elements must be sufficiently "rich" or "flexible", otherwise, the time required to compile or map circuit elements of a circuit design onto the logic elements may become unacceptably long or even down right impossible.
Today, the most highly complex integrated circuits, such as a microprocessor, pack hundreds of thousands of transistors into a very small area. To emulate even a portion of these highly complex integrated circuits would require a very large emulation system having a significantly larger number of reconfigurable logic elements that is of an order of magnitude greater than the emulation systems known in the art just a few years ago.
While there have been significant advances in integration as well as surface mounting technology at the same time, allowing more logic elements to be packed into the general purpose FPGAs and in turn mounted on circuit boards of substantially the same size, it is still impossible to build one of these large emulation systems with a handful of circuit boards. A large number of circuit boards must be employed. It is no longer uncommon to take days or even weeks to compile or map one of these highly complex circuit designs onto a large number of logic elements packaged in a large number of general purpose FPGAs and circuit boards interconnected in a conventional manner, even with today's high performance workstations. Thus, a new and innovative way of packaging and interconnecting these large number of logic elements is clearly desirable.
On the other hand, clearly not all circuit designers require these large emulation systems. Indeed, the market requirement spans a wide spectrum, from the low end entry level systems having a handful of circuit boards, to the intermediate systems having a moderate number of circuit boards, and the high end systems described earlier. Thus, from a manufacturer's perspective, it is further desirable that the new and innovative way of packaging and interconnecting the reconfigurable logic elements be scalable, and works well for the low end systems as well as the high end systems.
Furthermore, it is fully anticipated that integration and surface mounting technology will continue to advance, allowing even more dense integration and packaging. Thus, it is further desirable for the new and innovative way of packaging and interconnecting the reconfigurable logic elements to be easily extensible to take advantage of advances in these technologies.
As will be disclosed in more detail below, the present invention achieves these and other desirable results which will be apparent to those skilled in the art from the description to follow.